Digital-to-time converter (DTC) based fractional-N phase lock loops (PLL) have demonstrated low power consumption, low phase noise and good figures-of-merit compared to other fractional-N PLL architectures. DTC-based fractional-N PLLs can be realized in both digital PLL form and analog PLL form.
Both the digital and analog forms of DTC-based fractional-N PLLs require DTC gain calibration to identify the average resolution of the DTC. DTC gain calibration should be performed in the background while a PLL is running, as a fixed DTC gain value cannot be specified due to voltage and temperature variations as well as random mismatches. Without an accurate estimation of the DTC gain, a DTC-based fractional-N PLL would suffer from worse phase noise and worse fractional spurs.